The present invention relates to a semiconductor integrated circuit and a design apparatus thereof.
One of test facilitation techniques to overcome difficulties in testing large-scale complex semiconductor integrated circuits is a built-in self test (to be referred to as a BIST hereinafter). The BIST is widely used.
In the BIST, a BIST circuit arranged around a test target block in a semiconductor integrated circuit automatically generates a test pattern to be supplied to the test target block and analyzes the test result output from the test target block.
First, a semiconductor integrated circuit including a test target, i.e., a test target block is set in a test mode. In this mode, the input terminals of the test target block receive a test signal which is different from that in the normal operation, and the output terminals feed data also to the BIST logic.
A BIST control circuit to control a BIST circuit is initialized. Then, a predetermined number of BIST clocks are input to execute the BIST. During the BIST, a test pattern generated by a pattern generator is automatically input to the test target block.
A test result analyzer analyzes the test result output from the test target block and outputs an analysis result.
In the BIST, it is unnecessary to prepare a large amount of test patterns on an external tester memory. Hence, the cost of the tester is reduced. All operations are done in the device in synchronism with the BIST clock. The use of a high-speed BIST clock enables a test at a higher operation speed than the test operation clock of the tester. This allows a product test in an actual operation.
In a System-on-Chip (to be referred to as a Soc hereinafter) having a plurality of kinds of functional blocks (IP (Intellectual Property) cores), it is possible to independently test blocks by building a BIST in each of the logic core and memory core. This arrangement also allows to simultaneously test a plurality of blocks and shorten the total test time.
On the other hand, when a plurality of blocks are tested at the same time, power consumption upon the test tends to considerably increase.
Especially in the BIST, generally, the fault detection capability is enhanced by raising the activation efficiency of the circuit as compared to the normal operation mode. For this reason, even when power consumption during the system operation is suppressed below a prescribed value set in design, power consumption during the test may fall outside the guaranteed range of power design and cause an operation error due to voltage drop.
Hence, scheduling to decide the test execution sequence needs to be appropriately done. It is necessary to make the total power consumption of simultaneously executed tests fall within the prescribed range and optimize the test from the viewpoint of power consumption and test time.
However, simple scheduling may be unable to solve the problem of power consumption because when the test circuits of several blocks are being operated, other blocks may operate.
For example, to execute a memory BIST circuit at a high frequency, the timing must be adjusted by using a high-speed clock input during the system operation as the clock of the memory and using the same clock even for the memory BIST circuit.
However, the high-speed clock for the system operation also propagates to a system logic circuit. The logic circuit operates at random so that power consumption is generated in the part other than the test target. If the propagation range spreads, the power consumption of the overall semiconductor integrated circuit becomes too high to neglect.
To prevent this phenomenon, a clock switching circuit to suppress clock input is provided at the system clock diverging point to the logic circuit to prevent clock propagation to it during memory BIST execution.
However, adding a circuit to the high-speed clock path locally delays clock propagation to each path, resulting in an increase in difficulties in timing adjustment and an increase in the design time.
A reference that discloses a conventional BIST circuit is as follows.
Japanese Patent Laid-Open No. 2003-208331